Transistor Logic Lab: CMOS Gates & Adders

Interactive CMOS switch-level circuit simulator. Build logic gates, latches, and adders directly from NMOS and PMOS transistors with live current flow and truth table verification.

Lab Experiment 1 of 10Beginner

Pull-Down Channel Conduction

Observe how an N-channel MOSFET acts as a voltage-controlled switch. Positive gate voltage attracts electrons into an inversion channel, completing the path between Drain and Source.

Circuit Operating Principle

An N-channel MOSFET has three active terminals: Gate (G), Drain (D), and Source (S). With 0V on the gate, the channel remains non-conductive (OFF). When the gate voltage rises above the threshold voltage (+5V), an electric field inverts the substrate to create a conductive channel between Drain and Source (ON).

Experimental Procedure:

Step 1: Wire Gate Control

Connect Switch A output to the Gate (G) of NMOS Q1.

Hint: Click the right terminal of Switch A, then click the left terminal (G) of NMOS.

Step 2: Connect Power Rail to Drain

Connect VDD (+5V) to the Drain (D) terminal of the NMOS transistor.

Hint: Wire VDD rail to the top-right terminal (D) of NMOS.

Step 3: Connect Source to Output LED

Connect the Source (S) terminal of NMOS Q1 to the LED input.

Hint: Wire bottom-right terminal (S) of NMOS to LED in.

Need wiring reference?

Live Circuit Diagnostics

+5V High0V LowCurrent Flow

Circuit is idle. Toggle an input switch or connect wires to begin.

Schematic:0 components · 0 wires

Truth Table & Input Sequencer

No input switches detected in this circuit. Place an Input Switch from the palette or load a schematic to test binary truth vectors.

How it works

Digital integrated circuits are composed of billions of complementary field-effect transistor switches wired into logic networks. This tool provides an interactive Complementary Metal-Oxide Semiconductor (CMOS) switch-level model to simulate electrical conduction in real time:

NMOS Transistors (Pull-Down Network): Conduct between Drain and Source when the Gate is HIGH (+5V). When the Gate is 0V, the channel is cutoff (high impedance).
PMOS Transistors (Pull-Up Network): Conduct between Source and Drain when the Gate is LOW (0V). When the Gate is +5V, the channel is cutoff (high impedance).
CMOS Principle (Zero Static Current): Pull-up and pull-down networks are arranged such that VDD (+5V) and Ground (0V) never conduct simultaneously in steady state. Current flows only during logic transitions.

From this complementary pairing, we construct the universal NAND and NOR gates, combine them into XOR gates, add feedback to build SR Latches & Flip-Flops (Memory), and assemble them into Half Adders & Full Adders (Arithmetic).

Worked example

Constructing a 2-Input CMOS NAND Gate:

Pull-Up Network (Parallel PMOS): Connect two PMOS transistors (PMOS A and PMOS B) with their Source pins tied to VDD (+5V). Tie both of their Drain pins together to the Output node. If either Input A is 0 or Input B is 0, at least one PMOS turns ON, pulling Output to +5V (Logic 1).
Pull-Down Network (Series NMOS): Connect NMOS A and NMOS B in series: NMOS A Drain connects to Output, NMOS A Source connects to NMOS B Drain, and NMOS B Source connects to GND (0V).
Operation: The only way Output can be pulled to GND (0V) is if both NMOS A and NMOS B are turned ON simultaneously—which only happens when Input A = 1 AND Input B = 1.
Result:(0,0) → 1, (0,1) → 1, (1,0) → 1, (1,1) → 0. A complete physical NAND gate!

Common mistakes

Crowbar Short Circuits: Connecting an active pull-up path and an active pull-down path to the output at the same time. In physical silicon, this creates a near-zero resistance short between VDD and GND, causing destructive current spikes and thermal breakdown.
Floating (Hi-Z) Nodes: Leaving the output or transistor gate disconnected from both VDD and GND. Because MOS gates are isolated by a thin silicon-dioxide dielectric, a floating gate behaves like a tiny antenna capacitor, picking up stray electromagnetic noise and causing erratic toggling.
Inverting Gate Confusion: Forgetting that single CMOS stages are naturally inverting (producing NAND, NOR, and NOT). Building an AND or OR gate requires an additional inverter stage, consuming 6 transistors instead of 4.

Frequently Asked Questions

Why do modern computers use CMOS instead of TTL or NMOS-only logic?

Older logic families like TTL (Transistor-Transistor Logic) or NMOS with pull-up resistors drew constant current even when the circuit was idle. CMOS only draws power when transistors toggle between 0 and 1. Without CMOS, modern multi-core processors with 50+ billion transistors would melt from heat dissipation within seconds.

Why do we build NAND gates first instead of AND gates?

In silicon physics, NMOS conducts to GND and PMOS conducts to VDD. A single stage of complementary transistors inherently inverts the input signal. Therefore, NAND (4 transistors) and NOR (4 transistors) are simpler to fabricate than AND (6 transistors) or OR (6 transistors).

How does a logic gate 'remember' data in a Flip-Flop?

Memory is created through feedback. By wiring the output of one inverting gate back into the input of a second gate, and cross-coupling the second gate's output back to the first, the circuit creates a bistable loop. Even when external input pulses stop, the internal feedback loop continually reinforces the stored 1 or 0 state.

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Sources

Weste & Harris, "CMOS VLSI Design: A Circuits and Systems Perspective" (4th Edition).
Sedra & Smith, "Microelectronic Circuits" (Oxford University Press).
Mano & Ciletti, "Digital Design: With an Introduction to the Verilog HDL".

Results are for engineering assistance. Verify important calculations and check official datasheets. See the Engineering Disclaimer.